package system

import bus._
import yycore._
import chisel3._
import common.Constants._


   class Tile() extends Module {
      val io = IO(new Bundle {
         val imem = new CoreLinkIO(nWords * XLEN)
         val dmem = new CoreLinkIO(nWords * XLEN)
         val coh = Flipped(new CoreLinkIO(nWords * XLEN))
         val immio = new CoreLinkIO(XLEN)
         val dmmio = new CoreLinkIO(XLEN)
      })
      io := DontCare

      val yycore = Module(new MyCore())

      val icache = Module(new ICache())
      val dcache = Module(new DCache())

      yycore.io.imem <> icache.io.in
      dcache.io.coh <> io.coh
      dcache.io.in <> yycore.io.dmem

      // flush
      icache.io.flush := yycore.io.flush(0)
      //dcache.io.flush := yycore.io.flush(1)

      io.imem <> icache.io.out
      io.dmem <> dcache.io.out
      io.immio <> icache.io.mmio
      io.dmmio <> yycore.io.dmmio
   }